Forum Discussion
Occasional ContributorCan use double DDR3 IP in one FPGA?
Hello Sir,
One DDR3 EMIF IP will maximize 3 IO Banks. If it's uses a smaller interface width, then it's requires less IO Bank.
Both of the devices are able to support two EMIF IP. You can check in the EMIF Device Selector Tool to find the estimation of the IO Bank usage based on the number of EMIF IP.
You may visit to EMIF IP Support Center to download the tool; https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/emif-support.html
Some of the example projects that you can refer to is in Intel Development Kit.
- https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-sx.html
- https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html
Regards,
Adzim
Regular ContributorHello Sir,
One DDR3 EMIF IP will maximize 3 IO Banks. If it's uses a smaller interface width, then it's requires less IO Bank.
Both of the devices are able to support two EMIF IP. You can check in the EMIF Device Selector Tool to find the estimation of the IO Bank usage based on the number of EMIF IP.
You may visit to EMIF IP Support Center to download the tool; https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/emif-support.html
Some of the example projects that you can refer to is in Intel Development Kit.
- https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-sx.html
- https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html
Regards,
Adzim
