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NGagl's avatar
NGagl
Icon for New Contributor rankNew Contributor
7 years ago

Calibration failing for DDR2 Memory Controller on Cyclone V

I'm having trouble implementing the example project generated when instantiating a DDR2 interace on a Cyclone V device on a custom board. At this point, I am trying to create a soft memory interface...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Nick,

Assume you have key in all the correct DDR2 setting in DDR2 IP, then the easiest way to debug is to use DDR2 example design generated from DDR2 IP.

If example design passed - then most likely is your board design issue

If example design failed - then it could be DDR2 IP setting or board design issue.

Thanks.

Regards,

Deshi