Calibration failing for DDR2 Memory Controller on Cyclone V

Hi Deshi,

I've worked on this quite a bit and am still having calibration failures on the guaranteed read step on group 0. At this point, I have worked through the board skew parameters worksheet to determine and input the correct board skew parameters, I've closed the timing, and performed simulations to verify my board-level terminations, and I'm still getting calibration failures.

What would you recommend as a next step to testing this design and hopefully getting it to work? Is there anything else I can do to determine whether or not its a board-level issue or one with my vhdl?

Thanks,

Nick