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NGagl
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7 years ago

Calibration failing for DDR2 Memory Controller on Cyclone V

I'm having trouble implementing the example project generated when instantiating a DDR2 interace on a Cyclone V device on a custom board. At this point, I am trying to create a soft memory interface...
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NGagl
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7 years ago

dlim,

Thanks for the reply. I have verified that the DDR2 selection is not out of spec for the EMIF. At this point, I am working my way through the debug checklist, but am having trouble with the board skew parameter estimator. I will be out of the office for a week but will get back to you with those results when I can.

I have seen some confusing and/or conflicting information about termination for the DDR2 interface on the Cyclone - do I need a 100ohm resister to ground from the oct_rzqin pin? What is the default termination on the interface?

Thanks,

Nick