Calculate Maximum with DSP builder

I am a bit unsure what is the requirement of this design. If you just want to

find the maximum(or minimum) of a given sequence of data then you can do

that readily in HDL(I rather go simulink path for the really hard stuff).

For example if your signal is "data_in" and it is std_logic_vector(15 downto 0)

then to get the maximum value:

*****************************

signal max_pos : signed(15 downto 0);

------

data_in_signed <= signed(data_in);

------

process(reset, clk)

begin

if(reset = '1')then

max_pos <= (others => '0');

elsif(rising_edge(clk))then

if(data_in_signed > max_pos)then

max_pos <= data_in_signed;

end if;

end if;

end process;

maximum <= std_logic_vector(max_pos);

********************************

Similarly for minimum:

signal max_neg : signed(15 downto 0);

process(reset, clk)

begin

if(reset = '1')then

max_neg <= (others => '0');

elsif(rising_edge(clk))then

if(data_in_signed < max_neg)then

max_neg <= data_in_signed;

end if;

end if;

end process;

minimum <= std_logic_vector(max_neg);

You can use the reset to clear the value and restart at any point e.g. per packet.