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JLee25's avatar
JLee25
Icon for Contributor rankContributor
6 years ago

C10 HDMI VIP

Hi, I am testing the C10 GX HDMI VIP reference design. https://fpgacloud.intel.com/devstore/platform/18.0.1/Pro/cyclone-10-gx-hdmi-4kp60-with-video-and-image-processing-pipeline-reference-design/...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI Johnson,

You are right. For 32 bit DQ DDR3, we only need 256 bit width to interact with the frame buffer.

The existing design of 512 bits on the frame buffer is to reserved for future expansion plan.

Thanks.

Regards,

dlim