--- Quote Start ---
Might be. My first point was to clarify that a low-pass filter can be designed with the FIR II compiler, but fs/fc of 50k is only feasible as multi-rate design.
I agree with kaz, that IIR is the better choice in this case. I feeled obliged to mention, that IIR implementation with high fs/fc ratio involves some problems too. A standard digital implementation of the second order building block for 1Hz@50kS/s needs about 27 extra fractional bits in the internal registers to avoid quantization errors. But that's manageable.
I also agree that you should give a filter specification.
--- Quote End ---
Hi,
Interesting... how did you calculate the "27 extra fractional bits in the internal registers" from the 1Hz@50kS/s requirement?
I'm now working to simulate it in the Simulink environment using DSP builder. Will I see those kind of restriction?
Idan
Honored Contributor
