--- Quote Start ---
Hi,
In my application I need to implement high order Butterworth Low Pass filter to ~1Hz from 32bits, ~50ksps input signal. How can I evaluate the filter performance and estimate the resources for that sort of filter (size, memory, DSP Block, number of stages…, to select the right FPGA Cyclone V size)? I need to use some IP cores editor… (I will purchase the license, of course). The FIR II IP is only applying to Decimation filter and not for Butterworth kind of filter, right?
Thanks a lot,
Idan
--- Quote End ---
Butterworth IIR requires few mults and registers. I have also heard of FIR butterworth but it gets meaningless as the idea started from analogue era into digital equivalence and IIR did the job. your cutoff of 1/50k is too sharp for any FIR so I will go for iir definitely though will get nonlinear phase.
You can get butterworth coeffs from matlab "[b,a] = butter(n,Wc) then study it while still in matlab using freqz(b,a) then implement it on fpga.
Honored Contributor
