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corestar
Contributor
ContributorBug in Avalon-MM PCIe core for Non-Qword aligned writes
The "Avalon-MM Cyclone V Hard IP for PCI Express" does not appear to handle Non-Qword aligned writes correctly. I can't find anything in the datasheet that says only Qword aligned writes are allowed....
- Hi,
I see the misunderstanding. BAR 32/64-bit setting refers to address width. Data width is the native master width, can be 64 to 256 bit, in your design 64 bit. To see address and data presented to a 32-bit slave, tap the slave interface directly.
Regards,
Frank
Wincent_Altera
Regular Contributor
Regular ContributorHi
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