Hi Chee Pin!
Really? Do I really need to explain it?
- First what you described here: https://forums.intel.com/s/question/0D70P000006INUJSA4
- Valid is always high!!!!!!!
- Read request is not necessary! Why is there then a read request signal?????????????????????????
- Data changes one clock cycle after, the manual states 3!!!!!!!
- Reset signal seem not to be necessary for read
- The waveforms for reading in the manual shows a reset upfront!!!!!!!!!!
- Behavior between Quartus 15.1 and Quartus 17.1 is different but manual does not show any difference!
- Maybe even Quartus 18.1 behavior is different but there is no new document for that!
Best regards,
Erich
Occasional Contributor
