Forum Discussion
Altera_Forum
Honored Contributor
16 years agoYou may be causing yourself problems having that burst length of 128. With a pixel width of 24 that means 5 pixels to every write/read. That means that each memory master is going to try and write/read 640 pixels each burst. I'd have to do the math but with all your masters writing/reading you may be temporarily starving the CVI and CVO. Try reducing the burst size to 32.
Your original post said you had 3 paths (3xCVI->3xBuffer->3xCVO). Get one path working first. Also, set your frame buffers to triple buffering until you get things working. Jake