Contributor
Contributor
ContributorHi @NathanR_Intel ,
Yes, That was my specific question. 3.3.4 of user guide says the ATX PLL can drive the no. of non-bonded channels. But, I did't find any statement in the S-10 XCVR PHY user guide which states that L-tile XCVRs doesn't support bonding mode. If I configure XCVR L-tile native PHY in the platform designer tool with Bonded mode for GXT, I am not seeing any error message (for S-10 SoC dev kit) saying that Bonded mode is not supported for L-tile XCVRs. As I am possessing incomplete information regarding XCVR PHY bonded mode support, I am looking for a document support explicitly describing the Bonded mode is supported or L-Tile native PHY in S-10.
With regards,
HPB
ContributorHi @NathanR_Intel ,
As I know, Channel Bonding is the feature of PCS. I want to write a custom PCS, then whether I can write a custom logic to take care channel Bonding? What are the dependencies of channel bonding wrt PMA block?
With regards,
HPB
ContributorHi @NathanR_Intel ,
https://www.youtube.com/watch?v=PxAx_xR_iJA
In this training video "Building an Intel® Stratix® 10 FPGA Transceiver PHY Layer", the material says that Bonding mode can be configured for L tile / H-tile XCVR PHY.
With Regards,
HPB
