BFM Read from On Chip RAM

Okay, I got it. This on-chip RAM does not have both waitrequest and readdatavalid. It works on a pre-determined read latency. But as you said, the interconnect takes care of it:

onchip_ram (
        .clk         (clk_clk),                                    //   clk1.clk
        .address     (mm_interconnect_0_onchip_ram_s1_address),    //     s1.address
        .clken       (mm_interconnect_0_onchip_ram_s1_clken),      //       .clken
        .chipselect  (mm_interconnect_0_onchip_ram_s1_chipselect), //       .chipselect
        .write       (mm_interconnect_0_onchip_ram_s1_write),      //       .write
        .readdata    (mm_interconnect_0_onchip_ram_s1_readdata),   //       .readdata
        .writedata   (mm_interconnect_0_onchip_ram_s1_writedata),  //       .writedata
        .byteenable  (mm_interconnect_0_onchip_ram_s1_byteenable), //       .byteenable
        .reset       (rst_controller_reset_out_reset),             // reset1.reset
        .reset_req   (rst_controller_reset_out_reset_req),         //       .reset_req
        .address2    (mm_interconnect_0_onchip_ram_s2_address),    //     s2.address
        .chipselect2 (mm_interconnect_0_onchip_ram_s2_chipselect), //       .chipselect
        .clken2      (mm_interconnect_0_onchip_ram_s2_clken),      //       .clken
        .write2      (mm_interconnect_0_onchip_ram_s2_write),      //       .write
        .readdata2   (mm_interconnect_0_onchip_ram_s2_readdata),   //       .readdata
        .writedata2  (mm_interconnect_0_onchip_ram_s2_writedata),  //       .writedata
        .byteenable2 (mm_interconnect_0_onchip_ram_s2_byteenable), //       .byteenable
        .clk2        (clk_clk),                                    //   clk2.clk
        .reset2      (rst_controller_reset_out_reset),             // reset2.reset
        .reset_req2  (rst_controller_reset_out_reset_req)          //       .reset_req
    );

    altera_merlin_slave_translator# (
        .AV_ADDRESS_W                   (7),
        .AV_DATA_W                      (64),
        .UAV_DATA_W                     (64),
        .AV_BURSTCOUNT_W                (1),
        .AV_BYTEENABLE_W                (8),
        .UAV_BYTEENABLE_W               (8),
        .UAV_ADDRESS_W                  (32),
        .UAV_BURSTCOUNT_W               (4),
        .AV_READLATENCY                 (1), <---
        .USE_READDATAVALID              (0), <---
        .USE_WAITREQUEST                (0), <---
        .USE_UAV_CLKEN                  (0),
        .USE_READRESPONSE               (0),
        .USE_WRITERESPONSE              (0),
        .AV_SYMBOLS_PER_WORD            (8),
        .AV_ADDRESS_SYMBOLS             (0),
        .AV_BURSTCOUNT_SYMBOLS          (0),
        .AV_CONSTANT_BURST_BEHAVIOR     (0),
        .UAV_CONSTANT_BURST_BEHAVIOR    (0),
        .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
        .CHIPSELECT_THROUGH_READLATENCY (0),
        .AV_READ_WAIT_CYCLES            (0),
        .AV_WRITE_WAIT_CYCLES           (0),
        .AV_SETUP_WAIT_CYCLES           (0),
        .AV_DATA_HOLD_CYCLES            (0)
    ) onchip_ram_s1_translator (

I just ran the simulation on ModelSim and traced the waitrequest=0 and readdatavalid=1 signals generated by the Avalon translator connected to this on-chip RAM. The readdatavalid is produced properly the next clock cycle when data is ready to read but the BFM master still reads the previous clock cycle :confused: