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In my case, I know the latency of the RAM ahead of time (you can set it in QSys parameters, can be 1 or 2 clock cycles). I just need to tell the BFM master to wait for it.
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No, you're misunderstanding something, let me explain.
The Avalon-MM bus specification defines the bus transaction timing. In your case, you are interested in a read. A read is initiated by the bus master by asserting the read signal. The read transaction is accepted by the slave when it deasserts the waitrequest signal. The read data is then valid when the slave asserts readdatavalid. The Avalon-MM BFM knows these rules (that is what makes it a bus functional model), and so it issues the read, waits for waitrequest to deassert, and then waits for readdatavalid to assert, at which point it copies the read data into the BFM structure that you can access from your testbench.
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I went through the "Altera Verification IP Guide" and couldn't find which API sets the master wait time. I found this one:
get_response_wait_time()
Returns the wait latency for transaction in the response descriptor that has been
removed from the response queue. Each cycle in a burst has its own wait latency
entry.
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If you call this API function on the read response packet you get when you access your RAM, then the value should be 1, i.e., the readdatavalid signal asserted 1 clock after the transaction was accepted.
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This RAM transaction is a read transactions with no readdatavalid signal
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This is the part that is leading to your confusion :)
If the Altera on-chip RAM you are testing does not include a readdatavalid signal, then the Avalon-MM fabric can infer one from the settings in the _hw.tcl file, so although there is a readdatavalid, you cannot easily probe it in Modelsim.
I'd recommend testing a component that uses waitrequest and readdatavalid.
If this recommendation is beyond where you feel comfortable, let me know, and I'll take one of my existing components and make it into a standalone example for you.
Cheers,
Dave
Honored Contributor
