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There is a task in the tutorial that reads a slave address using the BFM master. The slave is onchip_ram. The problem is that there is a latency of 1 clock cycle for the data to be available on the bus after the read address is available. This task reads the current value on bus (at the moment when the address is up), not the next cycle of the data (which is what I need). How can I fix it (such as introduce a latency in the response)?
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The BFM task knows *nothing* about the Avalon-MM bus timing. The whole idea of BFMs is to create an abstraction where you do not have to care about signals at the bus-level, as that is taken care of by the BFM.
The task pushes a read transaction into the BFM transaction queue, and then waits for the BFM response queue to have data. This wait may take multiple clock cycles (hence the while loop).
Once the queue has a response, the response is popped off the BFM queue, and its data returned to the user.
I wrote another example that uses a BFM slave as well as the master. You could run that and setup the slave to have a larger number of wait-states to see how the BFM master still works correctly regardless of the number of slave wait-states between transaction acceptance and read-data availability. See this thread (Post# 25);
http://www.alteraforum.com/forum/showthread.php?t=32952&page=3 If you are having a problem with your specific simulation, post details (or a zip) and I'll try to help you figure it out :)
Cheers,
Dave
Honored Contributor
