BFM MM-Master Help for custom IP

What you're missing here, I think, is that a BFM is only for simulation in a tool like the included ModelSim-Intel FPGA Edition (or full ModelSim). There is no reason to open up a Platform Designer (aka Qsys) test bench system in Quartus or manually instantiate a BFM in code.

The easiest thing to do is create a Platform Design system with just your component in it by itself, exporting all the interfaces. Then select the "Generate Testbench" option (standard setting) you mention. This creates a test bench system design that automatically selects, configures, and connects the appropriate BFMs for testing your component (like you say, a master BFM to drive your slave component but also clock and reset BFMs as needed) including scripts for running a simulation in a simulation tool. You got the error you mentioned because you didn't have exported interfaces to connect to BFMs in the newly generated testbench system. It does create a new .qsys file, but this is really just for looking at how the testbench system is set up, not for generating or compiling in Quartus since it is not synthesizable.

You can use the generated test bench program or write a test bench program to control the BFM(s) using the simple API documented in the verification IP user guide (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_avalon_verification_ip.pdf).

See this online training for details: https://www.intel.com/content/www/us/en/programmable/support/training/course/oaqsyssim.html

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