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paramProd's avatar
paramProd
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5 hours ago

BDSL File Issue_FA

On a design with an AGIA040R39A some of the FHT are disabled.  We tried to modify the BSDL file using the “Preconfiguration BSDL Editor for Agilex 7 Devices with F-Tiles” as mentioned here: https://docs.altera.com/r/docs/683748/current/agilex-7-jtag-boundary-scan-testing-user-guide/agilex-7-bst-guidelines

This does modify the BSDL file, but the BSDL file it generates (BSR length 3077 bits) doesn't match the boundary scan register length we're detecting in the device (3061 bits).

We suspect this is because the BSDL editor doesn't include the options for disabling FHT12B or FHT13B.  Would disabling these parts of the device reduce the BSR length by 16 bits?  If so, can the BSDL Editor be updated, or a modified BSDL file be supplied?

2 Replies

  • ai_responder's avatar
    ai_responder
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  • paramProd's avatar
    paramProd
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    Good observation, and the clue is actually in the pin connection guidelines themselves. The documented ENB_GXF_FHT disable pins for Agilex 7 F-Series/I-Series are explicitly enumerated as FHT12A, FHT12C, FHT13A, and FHT13C — FHT12B and FHT13B are not listed in those guidelines. The pin connection guidelines document ENB_GXF_FHT[12A,12C,13A,13C] as the inputs that enable or disable FHT support in F-Tile, tied to VCCCLK_GXF when FHT channels are used, and to GND when not used. Agilex® 7 Device Family Pin Connection Guidelines The absence of 12B and 13B from that list strongly suggests the Preconfiguration BSDL Editor was built around the same enumeration, which would explain why it has no option to remove those cells.
    The Preconfiguration BSDL Editor is specifically designed to remove boundary scan cells from powered-down F-tiles to shorten the overall boundary scan length, and requires Tcl version 8.6 or above. Preconfiguration BSDL Editor for Agilex® 7 Devices with F-Tiles - Note.txt If your design has FHT12B and/or FHT13B physically powered down but the editor has no mechanism to exclude their cells, the generated BSDL will overestimate the BSR length — consistent with your 3077 vs. 3061 discrepancy.
    It's also worth being aware of a broader known limitation: boundary scan of F-Tile FHT transceiver channels is not supported in Agilex 7 FPGA devices when using Quartus Prime Pro software version 26.1 or earlier. The documented workaround is to bypass the F-Tile FHT transceiver channels in your boundary scan chain, and this problem is planned to be fixed in a future version of Quartus Prime Pro. Why does boundary scan fail or report length mismatches when including F-Tile FHT transceivers in the scan chain of Agilex® 7 FPGA devices when using Quartus® Prime Pro software version 26.1 or earlier?
    Additionally, there is a separate known issue at the JTAG instruction level: due to a problem with the boundary scan circuitry of the FGT transceivers, the EXTEST JTAG instruction cannot be executed directly. Agilex® 7 F-Series and I-Series Known Issue List This affects all Agilex 7 production devices (AGF and AGI OPNs), with no planned fix and no planned OPN change. Agilex® 7 F-Series and I-Series Known Issue List
    In summary: your hypothesis that FHT12B/FHT13B are not represented as disable options in the BSDL Editor is well-founded given the documented ENB_GXF_FHT pin list. The workaround path the documentation points to is bypassing those channels in the scan chain rather than relying on the editor to generate the correct length. To get the BSDL Editor updated to include FHT12B/FHT13B options, or to obtain a pre-corrected BSDL file for your specific OPN/configuration, that would require engaging Altera support directly with your device OPN and the specific FHT channel configuration.