Hi all I am experimenting with PCIe example designs. In example design there in AVMM master in one of the IP block which is connected to a AVMM agent port on on chip memory IP. I understand that during RTL compilation Quartus inserts necessary logic to make AVMM connection between these ports. For a design specific need i am interested in getting a copy of all AVMM signals at AVMM agent port. Purpose is to monitor all WR and READ activities and take action based on specific reads or writes.what will be the best way to achieve this? is there any IPs or capabilities available via Quartus?I am trying to avoid writing RTL for "AVMM middle man" module, which take request on its agent port and forwards using its master port and, when response is received it forwards that to original Master/requester.

Hi,May I know which device you are targeted ? Because each device and spec might be different.Generally if you wish to monitor the write and read activities without involving any RTL changing activity , I would suggest you can use below methodUsing Signal Tap Logic Analyzer2.1. Signal Tap Logic Analyzer IntroductionYou can monitor the write and read signal - those signal naming might be slightly different depends on the device.I would suggest to refer to respective user guide on your targeted deviceAdd a Signal Tap instance. Tap all AVMM signals at the agent port (command name will be address, writedata, readdata, write, read, chipselect, waitrequest, etc.). Use complex triggers to capture specific accesses. Export captured data for analysis.Using the System Console / In-System Sources and Probes 7.5.4. Using the In-System Sources and Probes ServiceCan read/write signals at runtime., BUT not a real-time HW response Hope that clarfied.Regards,Wincent_Altera

thank you Wincent for your reply, I am using Agilex7 FPGA.the AVMM master port is part of PCIe ip - and agent port at memory is intel onchip memory ip . Both are altera IP from ip catalog. the memory is mapped BAR0. in my application BAR 0 is acting as config area and based on read writes accesses to particular offsets some internal logic need to change FSM states. for this purpose i need to a copy of all AVMM agent port signal, Once I have copy of this signals, I can write my own RTL to monitor activities interesting to us and change internal FSM states as I wish.once the logic is developed I will need to do signal tap analysis to make sure my logic is working as intended, So your response regarding signal tap definitely helps, but I still need help on how can i get AVMM agent port signal copy so that I can write my own logic based on AVMM activities.thanks

Hi ,May I know which device that you targeted ? because for Agilex 7 we have F-tile for higher bandwidth , P-tile and R-tile for Gen5.At the same time for Agilex 7, we only provided AVST and MCDMA IP design example. For AVMM implementation , I assume this is your own custom design right ?About AVMM port signal information, I found some description in MCDMA user guide. 3.5. Config Slave (CS)3.5.2. 14 bit AVMM address formatIf you are asking about the naming of write and read signalYou can try to navigate it under the AVST user guide based on the tile that you are using https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/pcie-support.htmlNot sure if this is something that you looking at or not ? If not please let me knowRegards,Wincent

I am using MCDMA R-Tile Design Examples for Endpoint. https://www.intel.com/content/www/us/en/docs/programmable/683517/22-4/mcdma-r-tile-design-examples-for-endpoint.htmlon https://www.intel.com/content/www/us/en/docs/programmable/683517/25-1/avalon-mm-pio-using-mcdma-bypass-mode.html in figure 2 below Mem_PIO is mapped to BAR0. in my design since BAR0 is used as config area I need to write an RTL to monitor RD/WR traffic to "MEM_PIO"; and to do that I need access to AVMM agent port`s copy. for example BAR 0 offset 0x0 to 0x10h is my config area.Host copies "input data" at BAR0 offset 0x100h to 0x200h.host writes 0x1h to BAR0 offset 0x0h (part of config area) this means that data between offset 0x100h and 0x200h is valid and my design can use these input data to generate output data. Output data is copies to unique offset in BAR0.as you can see at step number my RTL design need to monitor accesses to BAR0, I can only write my RTL if i have access to AVMM agent port activities. I need to knowWhat BAR0 offset is accessed by host?is it read or write access?if its write what value is being written?My RTL design can only work I have copy of all accesses. My RTL design is not trying to intercept AVMM traffic or modify AVMM request or responses by any means. Its just looking at the activities and take action for internal logic when needed.So how do i get access to AVMM agent port?

Hi,Thanks for such clear and detail clarification.So you might need to check the AVMM agent port signal copy in order to take action for internal logic when needed.If that is the cases, perhaps you can check on 3.7. Avalon® -MM Agent AddressingLet me know if it is not clear, And I am happy to provide better clarification on that.Regards,Wincent

AVMM transparent bridge | Altera Community

12 Replies

Wincent_Altera
Regular Contributor
3 months ago
Hi Ankit,

Thanks for your reply, glad that the other specialist able to address your question, also thanks community expert - FVM who provide some valuable feedback.
If there is a further question, please do file a new forum thread , we will be there to assist.

Regards,
Wincent
Wincent_Altera
Regular Contributor
4 months ago
Hi,

I saw the question been address by our Quartus Software specialist under
https://community.intel.com/t5/forums/forumtopicpage/board-id/fpga-intellectual-property/message-id/30831#M30831
Is there issue related to PCIe that I can further address ?

Regards,
Wincent_Altera
- UserID4331231
  Occasional Contributor
  4 months ago
  The response on other thread was satisfactory.
  for this thread as user FvM mentioned I am trying to copy RAM HDP instances and save them as custom memory IP generated by me.
  I think this idea can work. I will update later on my findings.
FvM
Super Contributor
4 months ago
Hi,
possible solution, implement the AVMM agent as HDL component, e.g. by copying the IP implementation. Add code to tap AVMM interface signals.

AVMM to internal RAM is quite simple design, I've implemented various FIFO memories with special features.
FvM
Super Contributor
4 months ago
Hi,
there should be a link to design example files respectively a reference to development kit where it's shipped with
Wincent_Altera
Regular Contributor
4 months ago
Hi,

May I know which device you are targeted ? Because each device and spec might be different.
Generally if you wish to monitor the write and read activities without involving any RTL changing activity , I would suggest you can use below method

Using Signal Tap Logic Analyzer
2.1. Signal Tap Logic Analyzer Introduction
You can monitor the write and read signal - those signal naming might be slightly different depends on the device.
I would suggest to refer to respective user guide on your targeted device
Add a Signal Tap instance.
Tap all AVMM signals at the agent port (command name will be address, writedata, readdata, write, read, chipselect, waitrequest, etc.).
Use complex triggers to capture specific accesses. Export captured data for analysis.
Using the System Console / In-System Sources and Probes
7.5.4. Using the In-System Sources and Probes Service
Can read/write signals at runtime., BUT not a real-time HW response

Hope that clarfied.

Regards,
Wincent_Altera
- UserID4331231
  Occasional Contributor
  4 months ago
  thank you Wincent for your reply,
  I am using Agilex7 FPGA.
  the AVMM master port is part of PCIe ip - and agent port at memory is intel onchip memory ip . Both are altera IP from ip catalog. the memory is mapped BAR0. in my application BAR 0 is acting as config area and based on read writes accesses to particular offsets some internal logic need to change FSM states.
  for this purpose i need to a copy of all AVMM agent port signal, Once I have copy of this signals, I can write my own RTL to monitor activities interesting to us and change internal FSM states as I wish.
  once the logic is developed I will need to do signal tap analysis to make sure my logic is working as intended, So your response regarding signal tap definitely helps, but I still need help on how can i get AVMM agent port signal copy so that I can write my own logic based on AVMM activities.
  thanks
  - Wincent_Altera
    Regular Contributor
    4 months ago
    Hi ,
    
    May I know which device that you targeted ? because for Agilex 7 we have F-tile for higher bandwidth , P-tile and R-tile for Gen5.
    At the same time for Agilex 7, we only provided AVST and MCDMA IP design example. For AVMM implementation , I assume this is your own custom design right ?
    
    About AVMM port signal information, I found some description in MCDMA user guide.
    3.5. Config Slave (CS)
    3.5.2. 14 bit AVMM address format
    If you are asking about the naming of write and read signal
    You can try to navigate it under the AVST user guide based on the tile that you are using
    https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/pcie-support.html
    
    Not sure if this is something that you looking at or not ? If not please let me know
    
    Regards,
    Wincent

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AVMM transparent bridge

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