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UserID4331231
Occasional Contributor
Occasional ContributorAVMM transparent bridge
Hi all I am experimenting with PCIe example designs. In example design there in AVMM master in one of the IP block which is connected to a AVMM agent port on on chip memory IP. I understand that du...
FvM
Super Contributor
Super ContributorHi,
possible solution, implement the AVMM agent as HDL component, e.g. by copying the IP implementation. Add code to tap AVMM interface signals.
AVMM to internal RAM is quite simple design, I've implemented various FIFO memories with special features.
