Avalon Timing for onchip memory

Qsys should take care of all the master-slave interfacing - the whole point of using Qsys is that you do not need to worry about the IP to Avalon timing.

Just to answer your question though, the onchip RAM doesn't have waitstates, so in exclusive use (single master connection) the waitrequest signal seen at the master is always disabled. Also because onchip RAM is a parallel bus, where the address/data is available on a single clock cycle with zero waitstates for both read/write, burst mode does not exist for such slave.

Again, Qsys is able to adapt your master (as long it is an AvalonMM type) to the slave interface, and create additional pipelining/waitstates to match.