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So, from documentation I got only following instructions.
http://www.alteraforum.com/forum/attachment.php?attachmentid=10729&stc=1 All transfers of an Avalon-ST connection occur synchronous to the rising edge of the associated clock
signal. All outputs from a source interface to a sink interface, including the data, channel, and error
signals, must be registered on the rising edge of clock. Inputs to a sink interface do not have to be
registered. Registering signals at the source facilitates high frequency operation.
I am not an experienced fpga developer, but an electronic engineer. From timing diagram it seems that I should sample data at falling edge. But from documentation and following your sugestion It seems right to sample data at rising edge and to registering outputs synchronously at rising edges.
This last part seems not compliant to what you are suggesting for output data on the state machine. I don't understand if I am not following documentation or if there is a lack on it. Anyway official shared code from altera could provide the solution.
Hope I am getting right :)
Thank you Krasner.
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If you're doing things inside the the FPGA, on the same clock, for all logic you should be sampling on the rising edge of the clock. The timing analyser will tell you if there are any setup violations, which can then be fixed in your code, usually with more pipelining.
The timing diagram you see is a digital logic waveform, not a fully timed interface specification, because it is not needed.
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