Avalon Streaming sink and source state machines

Altera documentation is notoriously bad, at least in my experience. So try reading the latest versions of documentation.

Avalon streaming data is sampled on rising edge as is shown in your figure. Which part seems no compliant? Is it the FSM part?

Seeing as you are trying to make a Moore state machine you would have 2 state (state1, state2) and transitioning between these states depends on your input X.

To do this you need first sample your stream and store the value into reg X. Then your FSM would transition based on your X changing.

The first part will be the same as before:

wire [width-1:0] d;

reg [width-1:0] X;

assign d = data_in;

always @(posedge clk) begin

if (snk_valid) begin

X<= d;

end

end

Then we need to define the FSM:

a) define state and next_state

reg [1:0] state (since you have two states 01 and 10)

reg [1:0] next_state

parameter state1 = 2'b01;

parameter state2 = 2b'10; (just assigning values to our state names)

b) define how the FSM changes state. Here we use the combinatorial always block:

always @( state or X) //our sensitivity list is state or X

next_state = 0;

case(state) //now we look at what state comes next

state1: //lets say that if X = 0 then we keep the same state, if X = 1 we go to state2

begin

if( X == 1 )

next_state = state2;

else

next_state = state1;

end

state2:// same idea for state2

if (X == 1)

next_state = state1;

else

next_state = state2;

end

endcase

end

c) We defined next_state so we have to update state

always @(posedge clk)

begin

state <=next_state

end

d)Now we define what to do when we are in each state. Since we are outputing an avalon stream we want this to be clocked and i guess in sync with the incoming valid signal

reg dout;

always @(posedge clk) //clocked process

begin

if (snk_valid) begin //sync signal to valid of input

case(state) //again we will do a case statement for the states

state1:

dout <= "Some output"

state2:

dout <= "Some other output"

default:

dout< = 0;

endcase

end

end

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

So you see we have 4 subsections:

1) sample incoming data

2) define transitions of FSM states

3) update current state

4) define functions during each state

Let me know if these looks reasonable