Avalon Streaming sink and source state machines

Sampling streaming data is easy since it is synchronous to the clock. In an always block with the condition of posedge clk, you would check if your valid signal is asserted. Then you would read the data.

Something like this

wire [width-1:0] d;

reg [width-1:0] dout;

assign d = data_in;

always @(posedge clk) begin

if (snk_valid) begin

dout <= d;

end

end

You can add reset (negedge rst_n) to make the logic more robust.

For the FSM you need to set up your state machine in a combinatorial always block. It is similar to the one above (which is sequential) but instead of using the clock as your condition (sensitivity list), you will use state and the regs that affect your state. In this always block you will determine next_state based on current state and changes in your sensitivity list regs. Then you will need a second combinatorial always block that describes what to do when you enter each state (this is done by using the case statement).

This link has a good overview of FSMs in verilog: http://inst.eecs.berkeley.edu/~cs150/sp12/resources/fsm.pdf