Forum Discussion
ContributorAvalon Streaming Dual Clock FIFO
Hi,
Understood that. Could you try to use the simple adapter ST handshake clock crosser under the bridges and adapters section? I think you're connecting it correctly previously. Instead of using dual clock fifo under on-chip memory section, as it's embedded peripheral I'm not sure is there anything needs to take note when using it.
Regarding why booting slow when using 200mhz, you need to open a new thread target pcie to get the related pcie expert helps.
Thanks,
Regards,
Sheng
Super ContributorHi,
Understood that. Could you replace that iopll with clock source to check whether the problem is on the pll?
If the problem is on pll, then would need pll folk to look into this.
Thanks,
Regards,
Sheng
ContributorHi @ShengN_Intel,
I can confirm that with the 50MHz clock this design works:
With a verilog defined for the clock:
... // Qsys Top module assign sys_clk_50 = REFCLK_50; qsys_top soc_inst ( ... .clk_50_clk (sys_clk_50), ... ); ...
I would note, however, that I do not have another clock going faster than my main system clock to test with - which is why my application will be relying on a PLL.
What would you suggest to try now?
