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Altera_Forum
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8 years ago

Avalon-MM to LPDDR2 HMC IP not permitting burst counts larger than 4?

Hello, I'm using one of the Hard Memory Controllers on a 5CGXFC5C6F27C7 from the Terasic Cyclone V GX Starter Kit. The board has a single LPDDR2 chip. I've instantiated the IP, and can get it...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi.

I seem to have the same problem. I'm using Quartus 16.1.2. and DDR3 SDRAM Controller with UniPHY with Hard Controller. When modeling or seeing SignalTap II Logic Analyzer, I see that the burst larger than 48 does not reading too. Also I see pulsing avl_ready. But workaround didn't help me. https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08142013_467.html

Unfortunately I could not view your screenshots, they are too small.

Have you solved the problem?