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Altera_Forum
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8 years ago

Avalon-MM to LPDDR2 HMC IP not permitting burst counts larger than 4?

Hello, I'm using one of the Hard Memory Controllers on a 5CGXFC5C6F27C7 from the Terasic Cyclone V GX Starter Kit. The board has a single LPDDR2 chip. I've instantiated the IP, and can get it...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Just wanted to provide a quick update. After making my controller more configurable I was able to test more thoroughly. It appears burst sizes 1-7 work as expected. Bursts of 8 and higher are broken. The LPDDR2 RAM being utilized has configurable 4/8/16 native burst lengths. It's currently set to 8, which should make an Avalon-MM burst of 8 the most optimal length, but for some reason it doesn't work.