Avalon-MM slave shows constant high reg_busy signal (TSE IP).

HI,

Your understanding is correct that user needs to configure TSE MAC and PHY register first to initialize the IP core before you can use it.

Regarding reg_busy :

• This is output status signal from TSE MAC to user logic. You shouldn't assign any value to it as it's output status signal, not input signal.
• I am sorry for the confusion in the TSE user guide doc but what it means is - it's an indicator to tell user whether TSE MAC is busy processing something or not. When it's asserted, user shouldn't send further command to TSE MAC anymore. user command should only to sent when reg_busy is low indicating TSE MAC is ready to accept user command now.

Regarding why reg_busy never deasserted low :

• It's hard to tell what's wrong by looking at partial of your sim waveform
• I am not sure which FPGA product that you used but you can always checkout TSE example design to study the expected signal behaviour
• https://fpgacloud.intel.com/devstore/platform/?acds_version=any&ip_core=Ethernet
  • Filter by FPGA product family then by Ethernet IP
• https://www.intel.com/content/www/us/en/programmable/products/intellectual-property/ip/interface-protocols/m-alt-ethernet-mac.html
  • Doc -> reference design link

Thanks.

Regards,

dlim