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Altera_Forum
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14 years ago

Avalon_ mm_ master wrapper (vhdl)

Hello, I have written a code for CDMA Encoding and CDMA Decoding using VHDL Language. Now i have to create as a custom IP using component editor.Here i want a help regarding the avalon signals. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Dear Sir, When should we assert these signals.

1.read---> if "read=1" , generally what should happen,it reads read address . am i right?

2.write---> if "write=1"writes into some write address.

but i have a doubt in these following control signals:

1.readwaittime

2.readdatavalid

3.waitrequest

please tell something about these three signals correctly.what should happen ,when we assert which signals.

thanks in advance.