Avalon_ mm_ master wrapper (vhdl)

Dear Sir, When should we assert these signals.

1.read---> if "read=1" , generally what should happen,it reads read address . am i right?

2.write---> if "write=1"writes into some write address.

but i have a doubt in these following control signals:

1.readwaittime

2.readdatavalid

3.waitrequest

please tell something about these three signals correctly.what should happen ,when we assert which signals.

thanks in advance.