Avalon_ mm_ master wrapper (vhdl)

The nios cpu always does 32bit bus cycles, when it does read cycles all 4 byte enables are always asserted - this is independant of the implied data width of the instruction.

If your avalon slave only has 16 data lines then a 'bus width adapter' is transparantly added to the avalon switch fabric by the sopc builder/qsys.

This will generate two cycles into your 16bit slave for every access requested by the nios cpu. The write cycles will have appropriate byte enables asserted (possibly none of them), the reads will always have both byte enables asserted.