Forum Discussion
JPovo
New Contributor
New ContributorAvalon MM Master and Slave need to have the exact same signals?
Hello, I am using the "mem_if_ddr3_emif_0 - DDR3 SDRAM Controller with UniPHY Intel FPGA IP" to acces the DDR3 external memory. In Platform Designer (QSys), Quartus 18.1. I have my own readmaster c...
sstrell
Super Contributor
Super ContributorYou don't need to add them to your master if you don't want/need to do burst accesses. However, the interconnect will get generated automatically with logic to handle this burst signaling.
JPovoNew Contributor
New ContributorWell, I thought just so, but when I connect just: read, readData, waitRequest and address, the waitRequest goes up with read and never ends. However, if I hold read just for one cycle ignoring the waitRequest, the waitRequest then goes down together with read and the data appears a few cycles after - just like pipeline reading... (and my master didnt have readDataValid signal here)
