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sadad's avatar
sadad
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6 years ago

Avalon Interconnect Dynamic Bus Sizing and Bursts

Hello! My Avalon-MM master has 32bit data width and is bursting capable. Now i connect an Avalon-MM slave with 8bit data width which is also bursting capable. Will a 32bit read or write access to ...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

I look into the testbench again, why does your burst count in the slave showing 1 to 4 but your input of your master only shows 1? Did you manually write to the avs signal?

I imagine if your slave is a ram, your burst count cannot be control in the slave side avs. It should be only be control in the master avm but in your case, it is limited to 1 bit.

BInos's avatar
BInos
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6 years ago

are you the creator of this testbench?

because i have a 32bit datawidth avs master bfm and a 8bit datawidth slave bfm

=> the avalon interconnect will insert an width adapter.

this adapter should convert one 32bit transaction to one 8 bit burst transaction with bustcount 4.

=> the master avs does not need to be bursting capable.

=> the slave avs must be bursting capable (as in my qsys design)

PS: this forum software sucks