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sadad's avatar
sadad
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7 years ago

Avalon Interconnect Dynamic Bus Sizing and Bursts

Hello! My Avalon-MM master has 32bit data width and is bursting capable. Now i connect an Avalon-MM slave with 8bit data width which is also bursting capable. Will a 32bit read or write access to ...
KennyT_altera's avatar
KennyT_altera
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7 years ago

This is your simulation

  • BInos's avatar
    BInos
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    6 years ago

    Thats not the output of my testbench. Using Quartus 17.1 or 18.1.

    Your result shows a burstcount of 1 during write transaction. Mine shows correct burstcount of 4 when writing.

    Did you change some settings? I redownloaded my archive again from this thread and revalidated and confirmed my results.