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sadad's avatar
sadad
Icon for New Contributor rankNew Contributor
6 years ago

Avalon Interconnect Dynamic Bus Sizing and Bursts

Hello! My Avalon-MM master has 32bit data width and is bursting capable. Now i connect an Avalon-MM slave with 8bit data width which is also bursting capable. Will a 32bit read or write access to ...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

I make a comparison of the original waveform from the design example vs the modified version of your testbench.

Few things that i can observe is that, you read signal does not goes down, there should be a wait request goes down and the readdatavalid go up inorder to see the value.

Attached the screenshot.

  • BInos's avatar
    BInos
    Icon for New Contributor rankNew Contributor
    6 years ago

    wait request, readdatavalid has nothing to do with my issue at this point.

    my issue starts at the beginning of an read transfer.

    I marked the start of the write/read transactions:

    The rising edge of the read/write signal begins the burst. At this point the burstcount must already be correct!

    So the burstcount signal is wrong (should be 4) even before any of the wait request, readdatavalid signal come into play!