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sadad's avatar
sadad
Icon for New Contributor rankNew Contributor
6 years ago

Avalon Interconnect Dynamic Bus Sizing and Bursts

Hello! My Avalon-MM master has 32bit data width and is bursting capable. Now i connect an Avalon-MM slave with 8bit data width which is also bursting capable. Will a 32bit read or write access to ...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago
Is there any steps that I am missing? I am getting error: # ** Error: (vcom-11) Could not find master_0.altera_avalon_mm_master_bfm_vhdl_pkg. # ** Error (suppressible): test_program_pkg.vhd(8): (vcom-1195) Cannot find expanded name "master_0.altera_avalon_mm_master_bfm_vhdl_pkg". # ** Error: test_program_pkg.vhd(8): Unknown expanded name. # ** Error: (vcom-11) Could not find slave_0.altera_avalon_mm_slave_bfm_vhdl_pkg. # ** Error (suppressible): test_program_pkg.vhd(11): (vcom-1195) Cannot find expanded name "slave_0.altera_avalon_mm_slave_bfm_vhdl_pkg".
BInos's avatar
BInos
Icon for New Contributor rankNew Contributor
6 years ago

hm, must be something on your side, retested my steps without errors.

Did you make sure that:

"Open the qsys design hit "generate HDL" => make sure "Generate Simulation Model" is set to "VHDL"."

NONE would be wrong!