Avalon Interconnect Dynamic Bus Sizing and Bursts

Yes, it is based on the avalon verification demo testbenches: "avlmm_1x1_vhdl"

Open the qsys design hit "generate HDL" => make sure "Generate Simulation Model" is set to "VHDL".

=>

cd avlmm_1x1_vhdl

vsim -do run_simulation.tcl

=>

the simulation will output bfm errors like:

"WARNING: tb.dut.slave_0.mm_slave_vhdl_wrapper.<protected>: Pipelined read commands 2 > AV_MAX_PENDING_READS 1"

caused by the missing testbench implementation to control the slave bfm responses to master read requests.

This can be ignored for the proof of concept. The bustcount for read requests should be 4 even before the error happens.

See attached image:

Write Request seems ok, but Read Request shows only burstcount of 1.