Thank you for the course link I will try to take a look on it.
Meanwhile, I got a better "workaround". The BFM returned to the testbench system. If I add an onchip memory to my testbench system then the tool is forced to implement another interconnect which connects my IP and the memory with the BFM. This will generate readdatavalid signals from the IP.
Of course, the configuration of the BFM has to be adjusted.
altera_avalon_mm_master_bfm #(
.AV_ADDRESS_W (32),
.AV_SYMBOL_W (8),
.AV_NUMSYMBOLS (4),
.AV_BURSTCOUNT_W (1),
.AV_READRESPONSE_W (8),
.AV_WRITERESPONSE_W (8),
.USE_READ (1),
.USE_WRITE (1),
.USE_ADDRESS (1),
.USE_BYTE_ENABLE (1),
.USE_BURSTCOUNT (1),
.USE_READ_DATA (1),
.USE_READ_DATA_VALID (1),
.USE_WRITE_DATA (1),
.USE_BEGIN_TRANSFER (0),
.USE_BEGIN_BURST_TRANSFER (0),
.USE_WAIT_REQUEST (1),
.USE_TRANSACTIONID (0),
.USE_WRITERESPONSE (0),
.USE_READRESPONSE (0),
.USE_CLKEN (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.AV_BURST_LINEWRAP (0),
.AV_BURST_BNDR_ONLY (0),
.AV_MAX_PENDING_READS (4),
.AV_MAX_PENDING_WRITES (0),
.AV_FIX_READ_LATENCY (1),
.AV_READ_WAIT_TIME (1),
.AV_WRITE_WAIT_TIME (0),
.REGISTER_WAITREQUEST (0),
.AV_REGISTERINCOMINGSIGNALS (0),
.VHDL_ID (0)
)