Forum Discussion

HKana17's avatar
HKana17
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Available configuration with SDRAM Controller (altera_avalon_new_sdram_controller)

Hi,

I am looking for a way to configure the SDRAM Controller in Platform Designer system (altera_avalon_new_sdram_controller).

I want to use the configuration of the attached figure. This is of Renesas SH3 SDRAM Interface Guide. To double SDRAM capacity I place 2 chips of SDRAM. The data-bus width is still 16 bits instead of 32 bits. So DQ ports of the 2 chips are gathered to one. Address bus and control lines except RAS and CAS are common to 2 chips. The chip-enable lines are not separated.

But I can’t see such a configuration item in the parameter window of the IP. Can this SDRAM IP be applied to the configuration I wish?

Thanks in advance.

  • sstrell's avatar
    sstrell
    5 years ago

    Just because the CS lines are not separated in this diagram doesn't mean you couldn't specify two separate CS lines, assuming your board hasn't been designed yet. If your board is already designed and it matches the diagram, I don't think there's much you can do because, as you say, the IP only supports a single RAS/CAS.

3 Replies

  • HKana17's avatar
    HKana17
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Excuse me. I forgot to add some information.

    SDRAM means SDR SDRAM.
    My Quartus version is 18.1 lite.

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Just because the CS lines are not separated in this diagram doesn't mean you couldn't specify two separate CS lines, assuming your board hasn't been designed yet. If your board is already designed and it matches the diagram, I don't think there's much you can do because, as you say, the IP only supports a single RAS/CAS.

    • HKana17's avatar
      HKana17
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Dear sstrell,

      Thank you for your reply.

      Now here is a board mounted with many parts.

      I expected that 'FPGA IP' could support many multi-chip SDR/SDRAM configuration. But now I understand that the IP doesn't support that configuration, unfortunately.

      FPGA beginners might count on FPGA too much.

      Thank you again.