Forum Discussion
Occasional ContributorAvailable configuration with SDRAM Controller (altera_avalon_new_sdram_controller)
Just because the CS lines are not separated in this diagram doesn't mean you couldn't specify two separate CS lines, assuming your board hasn't been designed yet. If your board is already designed and it matches the diagram, I don't think there's much you can do because, as you say, the IP only supports a single RAS/CAS.
Super ContributorJust because the CS lines are not separated in this diagram doesn't mean you couldn't specify two separate CS lines, assuming your board hasn't been designed yet. If your board is already designed and it matches the diagram, I don't think there's much you can do because, as you say, the IP only supports a single RAS/CAS.
HKana17Dear sstrell,
Thank you for your reply.
Now here is a board mounted with many parts.
I expected that 'FPGA IP' could support many multi-chip SDR/SDRAM configuration. But now I understand that the IP doesn't support that configuration, unfortunately.
FPGA beginners might count on FPGA too much.
Thank you again.
