Honored ContributorHi, I am new to Altera solutions, but I was looking for an "easy way" to convert parallel TTL (even LVDS) to ASI Out. I found the ASI IP but I am not sure how easy it is to integrate, I mean, if it is "ready-to-use". Could anyone help me on this?
Regards, Thiago
Honored ContributorI'm also trying to make a SPI-ASI converter in FPGA in my mastering work.
So i'd like to use the open-core ASI evolution receiver on my system. The altera documention gives an overview at OpenCore Plus Evaluation of Megafunctions documentation. But i could not identify in Quartus II what are the steps necessary to compile and simulate the core. Any help is welcome. Thanks a lot, Best Regards.Honored ContributorUse MegaWizard and generate ASI core.
