danduanNew Contributor5 years agoArriaV thansceiver jitter tolerance Hi, my FPGA chip is 5AGXBA3D4F31C4, i want to ask some help for transceiver jitter tolerance. 1. For Receiver PHY, PMA includes CDR module, i want to know the CDR module jitter tolerance value,...Show More
CheepinC_alteraRegular Contributor5 years agoHi,Just would like to follow up with you on this. Thank you.
Recent DiscussionsConstraints not being picked for DCFIFOCyclone 10 GX IBIS-AMI modelsF-Tile Ethernet Hard IP (100G)Cyclone® 10 GX Avalon®-ST Interface for PCI Express example SimulationAgilex-7 AXI MCDMA for PCIe hang