Hi,
Using Arria V Starter Kit I'm trying following:
- Apply HD video to SDI input;
- Inside the FPGA: Receive HD video using standard SDI 14.0 IP module in RX mode;
- Inside the FPGA: Transfer it to another standard SDI 14.0 IP module in TX mode;
- Output the SDI re-encoded video from SDI output.
RX side separately works properly as well as the TX side.
The problem starts when I connect all together. The SDI RX decodes video with its own pixel clock based on its ref. clock. The SDI encoder produces its own pixel clock based on another ref. clock.
Thus I have two separate clock domains: one for RX side, another for TX side. The frequency is similar but not actually same, then any FIFO buffer I use for clock domains crossing overflows or underflows after some period of time.
Of course, I may build QSYS-based video processor including Video Frame Buffer in triple buffer mode.
It will work, however I need some much more simple solution. Is it existing?
Thanks