New Contributor
Frequent ContributorHi Mircea
Can you check if Table 40 of below doc is what you are looking for?
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-v/av_51002.pdf
For output pins, depends on clock or IO types, you can refer to below link:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/arria-v/pcg-01013.pdf
And map your device to the pin out file:
https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html
For skew handling, you can refer to timing constraint chapter 1.5.4 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altlvds.pdf
Thanks.
Eng Wei
New ContributorHi Eng Wei,
You only answered question 7.
If you don't know the answers for questions 1 to 6, please ask someone who knows, and get back to me.
Here are my questions again:
My 5AGXFB7H4F35C4 receives a 125MHz, ideal reference clock.
Using the internal PLL, I want to generate a 500MHz sampling clock for controlling 8 ADC chips.
1. What is the maximum clock frequency coming out of this device in LVDS? It's not through the ALTLVDS.
2. What would be the jitter?
3. What setting should I use, and what output pin for best performance? Please, give example of pin number and setting.
I also want to send a 2ns wide SYNC pulse on 8 outputs.
4. What would be the skew between the 8 outputs?
5. What is the minimum pulse width for LVDS outputs?
6. What setting should I use, and what pins for best performance? Please, give example of pin number and setting.
Thanks,
Mircea
