Arria II GX Devkit TSE RGMII Help

Hi all,

I've been struggling to get the ethernet port working on the Arria II devkit (after getting flash, DDR2, and DDR3 working). I am mimicking the code found in bts_config, but using vhdl, qsys, and quartus 11.0sp1. Just aiming to get the simple socket server running. The pre-loaded webserver works on power-up, so the HW is good. Here is the startup output Simple Socket on my fpga:

INFO    : TSE MAC 0 found at address 0x00001400
INFO    : PHY Marvell 88E1111 found at PHY address 0x00 of MAC Group
INFO    : PHY - Automatically mapped to tse_mac_device
INFO    : PHY - Restart Auto-Negotiation, checking PHY link...
INFO    : PHY - Auto-Negotiation PASSED
MARVELL : Mode changed to RGMII/Modified MII to Copper mode
MARVELL : Enable RGMII Timing Control
MARVELL : PHY reset
INFO    : PHY - Checking link...
INFO    : PHY - Link not yet established, restart auto-negotiation...
INFO    : PHY - Restart Auto-Negotiation, checking PHY link...
INFO    : PHY - Auto-Negotiation PASSED
INFO    : PHY - Link established
INFO    : PHY - Speed = 100, Duplex = Full
OK, x=0, CMD_CONFIG=0x00000000
MAC post-initialization: CMD_CONFIG=0x04000203
 RX descriptor chain desc (1 depth) created
mctest init called
IP address of et1 : 0.0.0.0
DHCP timed out, going back to default IP address(es)

It appears that the dhcp request is not being transmitted. The ENET TX led blinks a few times during this process, so there is at least an attempt to transmit the packet.

After scouring the forums/web, I have not been able to nail down the issue. Issues I have noticed in old posts that may or may not affect 11.0sp1:

• The PHY expects clock to be skewed, but this can be fixed by writing to a PHY reg with MDIO. It appears "Enable RGMII Timing Control" is doing that.

• Simple socket must be modified for RGMII.

• RGMII does not support 10/100 speeds.

I'm a little frustrated that Simple Socket doesn't "just work" on an official Altera devkit.

Any ideas on what I could be doing wrong? If someone has it working with qsys and quartus 11.0[sp1], I would love to see code or at least hear about any changes you needed to make to defaults.

When I get this working, I plan on posting files for a skeleton project with SRAM, DDR2, DDR3, and ethernet working.

Thanks for any help.