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diddi1057's avatar
diddi1057
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Arria 10 transceiver ATX PLL unlocked, when reference clock not present during device configuration

Hi all, please refer to attachment pdf .... Thanks
  • diddi1057's avatar
    diddi1057
    4 years ago

    Hi,

    good news:

    1. I have successfully simulated design in Modelsim -> ATX PLL relocked after REFCLK is present ->o.k.

    2. I have successfully downloaded design to hardware -> ATX PLL relocked after REFCLK is present ->o.k.

    Thank's for your advice!

    Regards

    diddi1057

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Thanks for your update and sharing. I am able to run the simulation now and observe similar waveform. As I look into your transceiver_sfp.vhd, I observed that seems like you are not enabling the reconfiguration interface of the ATX PLL. Only the Native PHY reconfiguration interface is enabled and connected. To recalibrate the ATX PLL, you would need to write to the ATX PLL reconfiguration interface.


Can you try to enable the reconfiguration interface of the ATX PLL and perform the ATX PLL recalibration registers read/write process to see if it works?


Thank you.


diddi1057's avatar
diddi1057
Icon for New Contributor rankNew Contributor
5 years ago

Hi,

thanks for info! Guess thats the issue. Will try on next Monday and give you my feedback.

This was not clear in the documentation for me.

Regards

diddi1057