Arria 10 transceiver ATX PLL unlocked, when reference clock not present during device configuration

Hi,

Thanks for your update and sharing. I am able to run the simulation now and observe similar waveform. As I look into your transceiver_sfp.vhd, I observed that seems like you are not enabling the reconfiguration interface of the ATX PLL. Only the Native PHY reconfiguration interface is enabled and connected. To recalibrate the ATX PLL, you would need to write to the ATX PLL reconfiguration interface.

Can you try to enable the reconfiguration interface of the ATX PLL and perform the ATX PLL recalibration registers read/write process to see if it works?

Thank you.