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diddi1057's avatar
diddi1057
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Arria 10 transceiver ATX PLL unlocked, when reference clock not present during device configuration

Hi all, please refer to attachment pdf .... Thanks
  • diddi1057's avatar
    diddi1057
    4 years ago

    Hi,

    good news:

    1. I have successfully simulated design in Modelsim -> ATX PLL relocked after REFCLK is present ->o.k.

    2. I have successfully downloaded design to hardware -> ATX PLL relocked after REFCLK is present ->o.k.

    Thank's for your advice!

    Regards

    diddi1057

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Thanks for your update. Your steps tally with those described in the user guide. I checked with register map and do not spot any anomaly. Just to check with you when you are doing the same steps in hardware, do you see the pll_cal_busy go high after triggering recalibration?


Can you share with me a simple test design with one channel Native PHY + ATX PLL + reset controller which could replicate your observation in Modelsim? I would like to further look into it.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin



  • diddi1057's avatar
    diddi1057
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    thanks for your answer. Will try do give you the required info next Monday!

  • diddi1057's avatar
    diddi1057
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    attached the simple simulation project with one channel Native PHY + ATX PLL + reset controller. Please refer to atx_pll_simu.pdf inside project for instruction.

    I have to check again the same steps in hardware, if pll_cal_busy go high after triggering recalibration ...

    Best regards

    diddi1057