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sl242's avatar
sl242
Icon for New Contributor rankNew Contributor
2 years ago

Arria 10 PCIe, wrong frequency in the timing analyzer.

Hi, We are using the Hard PCIe in Arria 10 with Hard IP mode is set to "Gen3 x2, Interface 128bit, 125 MHz". The communication works fine, but the coreclkout_hip frequency is not displayed correctly...
Pcie
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago
Hi,
timing analyzer isn't responsible for "wrong" clock frequency, it's only reporting clocks specified in your design.
I agree that hip_coreclock should be 125 MHz, question is how you managed to get 156 MHz in your design. How was the design created, is it based on PCIe AVMM endpoint design example?