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Ursa's avatar
Ursa
Icon for New Contributor rankNew Contributor
5 years ago

Arria 10 PCIe Write DMA Descriptor Controller Registers

Dear All,

I have a simple question but it is important to me and I didn't find an answer in the doc of ug_a10_pcie_avmm.

I think the WR_TABLE_SIZE register is allowed to change on the fly(not only in the initialization stage) by host driver, I just wanted to know if it can take effect at once after changing at anytime. Am I right?

Who can give me the answer yes or no? Thank you very much.

Best regards,

Ursa

4 Replies

    • Ursa's avatar
      Ursa
      Icon for New Contributor rankNew Contributor
      5 years ago

      @Deshi_Intel Thanks Deshi,

      Maybe my wording "on-the-fly" was not accurate, further ask, thus can I change this register in the gap time between two transfers? I just hope the entries of descriptor table can be dynamically changed in run time. Are there any methods?

      Best regards,

      Ursa

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI,


    If you are referring to "in between 2 transfer" then maybe it's still possible.


    Anyway, I encourage you to test it out in hardware to be sure.


    Thanks.


    Regards,

    dlim


  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI,


    It's been some time since I last heard from you. I hope you have find the answer by running test run to verify it


    For now, I am setting this case to closure.


    Feel free to post new forum thread if you still have enquiry in future.


    Thanks.


    Regards,

    dlim