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lcy2000's avatar
lcy2000
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8 months ago
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Arria 10 PCIe Gen 3 stuck at Equalization.Phase3

Hi, I'm writing a design with Arria 10 AVST PCIe IP (Quartus 24.3). Currently we have encountered equalization problem at PCIe Gen3. We are using A10GX1150 DevKit as an add-in card attached to a...
Pcie
  • Wincent_Altera's avatar
    Wincent_Altera
    7 months ago

    Hi ChenYang,

    In my understanding of PCIe, contrary to MalfTLP, BadTLP is a much more underlayered concept with a only a few reasons to trigger: (1) Link CRC error (2) Sequence Number error. (Refer to PCIe 3.0 Spec, Figure 3-17, Page 185/860)
    >> Okay

    >> Another that that you could check will be

    • Do you check if your endpoint has received the 8 required consecutive TS2's ?
    • But before it is able to complete sending 16 TS2s, the downstream port sends EIEOS and then starts sending TS1 ?
    • Based on my experience, once it meet sending 16 TS2, it shall transition to Recovery.idle since the requirement for that transition are meet >>Recovery.equilization phase X >> L0.

      Regards,
      Wincent_Altera
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
7 months ago

Hi,


I wish to follow up with you about this forum thread.

Do you have any further questions on this matter ?


Regards,

Wincent_Altera


  • lcy2000's avatar
    lcy2000
    Icon for New Contributor rankNew Contributor
    7 months ago

    Hi Wincent,

    Thank you for your advice for moving forward. They are be of great help.

    After a simple field test, we has initially confirmed that tx_st_valid cannot be deasserted right in the middle of a TLP and they can lead to BadTLP errors as the TLP is not transferred to the IP correctly. So I believe this case can be closed now.

    Sorry for delayed response due to a national holiday from 5.1 to 5.5.

    Chenyang