Arria 10 partial reconfiguration thru JTAG debug mode time out. No way to program the partial reconfiguration .rbf file. Please help!

1. Why does the PR .rbf programming needs to lower the TCK frequency but regular .sof programming does not (it was using 24MHz programming .sof successfully).

This is because SOF programming is just accessing the configuration block with PR.rbf proramming is making use of virtual JTAG to access the PR block. When accessing through virtual JTAG, the timing will be more worst.

1. Is the Intel FPGA devices' altera_reserved_tck the one connected to JTAG tck (just to confirm, though it looks it should be)? If so, what is the maximum frequency allowed in .sdc to constrain it?

Yes, but it will depends on your board connection to the JTAG. If you are using blaster cable then the timing will be more worst even if you set it in SDC.

1. For PR Controller configured as internal host, between using JTAG debug mode for PR programming and using PCIe thru PR Controller's Avalon Memory Mapped interface for PR programming, how fast will the PCIe thru PR Controller's Avalon Memory Mapped interface? Assuming the JTAG TCK is 6MHz and JTAG debug mode for PR programming speed is 1, for small PR persona, what is the speed ratio for PCIe thru PR Avalon vs JTAG debug mode for PR? And for large (very large) persona, what is the speed ration for PCIe thru PR Avalon vs JTAG debug mode for PR?

It will depend on your PCIe throughput. I do not have any ratio but PCIe can run in GByte/s while JTAG is only 6Mbit/s.